1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
High-integration of integrated circuits with a semiconductor device, in particular, a MOS transistor which is a field-effect transistor having a gate electrode with a MOS (metal-oxide semiconductor) structure is advancing well. Together with advancement of high-integration, microfabrication of such MOS transistor used in the integrated circuit is advanced in the range of a nano order. When an inverter circuit (a NOT circuit) which is one of basic circuits of digital circuits is configured by using a MOS transistor, if microfabrication of the MOS transistor advances, it becomes difficult to suppress any leak current, and the reliability is deteriorated because of a hot-carrier effect. Moreover, because of the requisition of ensuring a necessary current amount, reduction of an occupy area of the circuit is not accomplished. In order to overcome such problems, there is proposed a Surrounding Gate Transistor (SGT) which has an island semiconductor layer having a source, a gate, and a drain arranged in the vertical direction relative to a substrate and which has a structure that the gate surrounds the island semiconductor layer, and there are also proposed CMOS inverter circuits using such SGT (S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE JSSC, Vol. 30, No. 9, 1995.).
The inverter circuit which is a basic circuit of digital circuits includes a p-channel type MOS transistor (pMOS transistor) and an n-channel type MOS transistor (nMOS transistor). Because the mobility of a hole is half of that of an electron, it is necessary in the inverter circuit to make the gate width of the pMOS transistor twice as much as that of the nMOS transistor. Accordingly, a conventional CMOS inverter circuit using the SGT includes two pMOS SGTs connected in series and an nMOS SGT. That is, a conventional CMOS inverter circuit using the SGT includes three island semiconductors. That is, the conventional CMOS inverter circuit using the SGT includes three island semiconductor layers. When a CMOS inverter circuit using the SGT is configured by three island semiconductor layers in this way, such configuration may interfere with accomplishment of high-integration of semiconductor devices.